This invention generally relates to microprocessor and integrated circuit design techniques and specifically relates to the characterization of the noise sensitivity of integrated circuits.
Signal noise, line loading, and line coupling all contribute to signal degradation and cause much concern in the design and production of high speed Very Large Scale Integrated (VLSI) circuits. The effects of these phenomena are especially troublesome in the design of circuitry comprising numerous closely packed signal lines and densely packed logic circuits. To achieve minimum size and maximum design of integrated circuits involves a lengthy phase of design optimization followed by multiple design iteration. During design validation, a database representing the proposed integrated circuit is used to model the proposed silicon integrated circuit as closely as possible before a prototype or production integrated circuit is manufactured. The model of the integrated circuit is used to test and verify performance of the design and to identify and avoid potential and actual problems and the issues which are expected to occur once the integrated circuit is manufactured.
In accordance with Moore""s law, miniaturization of the integrated circuits and the wires which connect the various transistors on an integrated circuit must support the doubling of circuit density every 18 months. State of the art processors utilizing 0.18 micron and smaller feature sizes, cramming tens-of-millions of transistors on a single die, have between six and eight layers of metal used for wires interconnecting the underlying logic and transistors. In an effort to reduce the resistance associated with these wires, the width of the wires has been decreased to maintain compatibility with ever decreasing feature sizes, while the individual wires have grown in height. This reduced resistance allows an increase in connecting speed between transistors. However, these modifications in the width and height of the wires also affect interferences associated with neighboring wires.
In densely packed 0.18 micron and smaller integrated circuits, the capacitance effects between neighboring wires is difficult to accurately predict. Capacitance effects between wires can be impacted by a change in the direction of current in neighboring wires, the amount of current in neighboring wires, and the accumulative effects of neighboring wires within a specific distance. This interference is the result of the parasitic capacitance which is a product of the electric field between wires. This static electric field is caused by a voltage potential between two conductors when an insulator is located between the two conductors, resulting in capacitor coupling of the wires.
Capacitance loading can also have an adverse effect on signals carried on wires which were intended to maintain a constant voltage. The capacitance loading will effectively superimpose an additional current on the wire that is required to maintain the constant voltage and may result in a voltage spike which must be absorbed by the components (e.g., signal driver or signal receiver) connected to this wire. These voltage spikes may result in circuit failures. A wire in a VLSI circuit is usually viewed as having a driving circuit (a driver), the wire, and one or more receiving circuit (a receiver). If these voltage spikes reach the receivers connected to the effected or victim wire, which are required to maintain a constant voltage, the receiver may switch states within the dense wire environment of an integrated circuit resulting in a circuit failure.
If these loading effects are identified early, they may be prevented by spacing the wires further apart, increasing the driver strength (e.g., current driving capacity) or by making the receiver less sensitive to a voltage spike. Sensitivity to noise or noise problems are typically identified by the receiver""s response to the voltage spike. If the receiver ignores the voltage spike the noise problem may be ignored, because it does not cause a malfunction in the integrated circuit. However, if the voltage spike causes an adverse reaction in the receiver, the interference is at such a level that it must be resolved.
Systems and methods for investigating electrical characteristics of a multi-level interstructure are known. Such systems use complicated algorithms for simulating a circuit. The process is complicated by the fact that adjacent interconnects, or wires, sometimes follow non-parallel paths. Another complexity is that there is a non-linear relationship between some process variables and electrical characteristics. For example, the relationship between capacitance and the space between adjacent interconnects, or wires, is non-linear. Consequently, the computation and simulation procedures are complex and are typically performed using Electrical Design Automation (EDA) tools. For example, HIVE is a software package that performs 2D numerical field simulations for interconnects having given geometries to arrive at the closest-fit analytical functions. As another example, Simulation Program with Integrated Circuit Emphasis (SPICE) is a software package that is commercially available for simulating inter alia electrical performance of complex Very Large Scale Integrated (VLSI) chips. SPICE requires inputs in the form of a SPICE subcircuit datafile, known in the art as a xe2x80x9cSPICE deckxe2x80x9d which numerically characterizes and describes the value and type of every conductor and component of the VLSI chip.
Many common computer simulators are also variations of the simulator tool SPICE. These programs typically operate by accepting circuit frequency response parameters, either directly from a Computer Aided Design (CAD) package, a simulator (using discrete frequencies to directly measure frequency response of a circuit prototype) or other means. Based upon these parameters, the simulator is then typically used to, simulate special signal conditions for the circuit which are usually not discrete frequencies, i.e., to predict transit responses in an integrated circuit. The computer based simulator typically use numbers which represent test input signals, e.g., initial voltages, currents and frequencies. The simulators are then usually used to conduct a time based analysis of responses to the input signal conditions of the different measurement points of the circuit. These tools can be used to determine the noise characteristics and sensitivity of circuit designs.
While numerous SPICE simulations can accurately simulate the operation of the integrated circuit, the required number of SPICE simulations is expensive both financially and computationally. The SPICE simulator accurately simulates wires and circuits with respect to their voltage and current behavior. However, in order to identify potential noise problems on an integrated circuit, numerous SPICE simulations must be performed. In these numerous SPICE simulations, variables such as the switching speed of neighboring wires, the distance between the aggressor wire and the victim wire, the length of the victim wire which runs parallel to the aggressor wire, the strength of the driver, and the sensitivity of the receiver must all be known and possibly varied to adequately investigate the potential noise problem. To accurately determine the extent of the noise problem in a typical LSI or VLSI circuit literally millions of SPICE iterations would need to be performed. Normally, simplifying assumptions are made to reduce the number of SPICE iterations which must be performed. These simplifying assumptions may impose restrictions upon the design itself. For example, restrictions may be imposed on wire spacing, the number of stages of inverters used to reject voltage spikes in receivers, the shielding required to reduce or eliminate line capacitance, and other such integrated circuit design limitations may be imposed. These limitations may result in a less than optimal design.
A need exists for a system and methodology that will analyze integrated circuits with xe2x80x9cSPICE-likexe2x80x9d accuracy at a fraction of the cost and computational intensity required by SPICE or similar full-featured circuit simulator. A further need exists for the identification of interference determining parameters or criteria that can be used to classify receivers within an integrated circuit as either being susceptible to noise interference or predicted to be operating within their design limitations.
This need and other features and technical advantages are achieved by a method of determining noise characteristics of a circuit of an integrated circuit which includes the steps of classifying the circuit from the topology of the circuit to provide a circuit classification and measuring circuit parameters of the circuit to provide circuit parameter measurements. The method of determining noise characteristics further includes retrieving prestored noise characteristics using the circuit classification and the circuit parameter measurements and calculating a noise response of the circuit using the prestored noise characteristics. The step of classifying the circuit may be performed for each input terminal of the circuit and may further comprise the step of identifying each input as one of a invertor, a NAND gate, a NOR gate or a dynamic circuit. The step of measuring circuit parameters may include measuring a bad capacitance, determining a pn ratio, and counting a number of input terminals. The method may also include the steps of precalculating default schematics for common circuit types, identifying circuit parameters for each of the default schematics, sweeping the circuit parameters through a set of discrete values, calculating a noise response for each of the noise characterizations, and storing default schematics, circuit parameters and the noise responses for later use.
In another embodiment, the invention includes a tool for identifying noise responses for circuits within an integrated circuit which includes a circuit identifier which identifies a target circuit, and a circuit parameter identifier which identifies parameters for the target circuit. The tool further comprises a controller configured to lookup in a prestored table noise characteristics for the target circuit and the parameters, and a noise determiner which displays the noise characteristics for the target circuit with the parameters. The circuit parameter identifier may operate on each input terminal of the circuit. The circuit identifier may identify the target circuit as one of an inverter, a NAND gate, a NOR gate or a dynamic circuit. The circuit parameter identifier may identify a bad capacitance of each of the input terminals of the target circuit, a pn ratio of each of the input terminals of the circuit, and/or the number of input terminals of said target circuit.
Another embodiment of the current invention includes a tool for determining noise characteristics of an integrated circuit which includes means for classifying the circuit from the topology of the circuit to provide a circuit classification and means for measuring circuit parameters of the circuit to provide circuit parameter measurements. The tool includes the means for retrieving prestored noise characteristics using the circuit classification and the circuit parameter measurements and means for calculating a noise response of the circuit using the prestored noise characteristics. The means of classifying the circuit may operate for each input terminal of the circuit, and may identify each input as one of an invertor, a NAND gate, a NOR gate or a dynamic circuit. The means for measuring circuit parameters may include a means for measuring a bad capacitance, a means for determining a pn ratio, and/or a means for counting a number of input terminals. The tool may further include a means for precalculating default schematics for common circuit types, a means for identifying circuit parameters for each of the default schematics, a means for sweeping the circuit parameters through a set of discrete values, a means for calculating a noise response for each of the noise characterizations, and a means for storing default schematics, circuit parameters and the noise responses for later use.
It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.